1. Field of the Invention
The present invention relates to a block selection circuit, and more particularly, to a block selection circuit capable of improving speed of the block selection, and improving convenience of a simulation, as a reference fuse block is comprised to output a reference signal later than or at the same time to decision signals outputted from fuse blocks and a spare row enable signal is generated later than the decision signals by using the reference signal, in order to remove delay components.
2. Discussion of Related Art
A memory selects one block of a plurality of blocks comprised of thousands of word lines by using higher bit of row address and a specific word line of thousand of word lines in the block by using lower bit of row address. In addition, redundancy word lines replace defective word lines which occur fail, and a repair information is stored in the memory according to a fuse cutting. Accordingly, a block selection circuit selects a block in accordance with a block information determined by an external address. And also the circuit selects a block by whether the external address corresponds to the word lines replaced with the redundancy word lines, which means fuse cutting states. FIG. 1 is a circuit diagram illustrating the conventional block selection circuit.
Referring to FIG. 1, each of a first fuse block 11 and a second fuse block 12 includes a plurality of fuses and stores information of repair address according to fuse cutting states. Further, the first fuse block 11 and the second fuse block 12 distinguish whether an inputted address which has been decoded is the repair address or not by inputting an initiated signal wlcz, a decoding signal bax2<0:1> and a decoding signal bax01<0:3>. Here, the initiated signal wlcz is a signal for initializing the block selection circuit. And, when the external address is 3 bits, the decoding signal bax2<0:1> is a signal decoded higher 1 bit of the external address, and the decoding signal bax2<0:3> is a signal decoded lower 2 bits of the external address. As a result, the block is selected by the decoding signal bax2<0:1> and specific row word lines of the selected block are selected by the decoding signal bax01<0:3>. For instance, when a decoding signal bax2<0> is high level, an upper block is selected, and when a decoding signal bax2<1> is high level, a lower block is selected. Meanwhile, the decoding signal bax2<0> and the decoding signal bax2<1> are generated by decoding the higher 1 bit. Therefore, they may not become high level at the same time. Furthermore, when the input address is the repair address, the first fuse block 11 and the second fuse block 12 output decision signals xsRed_up, and xfsRed_dn of high level. When the input address is not the repair address, the first fuse block 11 and the second fuse block 12 output decision signals xsRed_up, and xfsRed_dn which are transited from high level to low level. The decision signals xfsRed_up, xfsRed_dn outputted from the first fuse block 11 and second fuse blocks 12 are respectively reversed by a first inverter I11 and a second inverter I12, and then become spare row enable signals sre_up, sre_dn. When the input address is identical to the repair address stored in the first fuse block 11 and the second fuse block 12, the spare row enable signals sre_up, sre_dn are respectively transited from low level to high level. The spare row enable signal sre_up, sre_dn are inputted in a NAND gate 13, and an output signal of the NAND gate 13 is reversed by a third inverter I13 and then becomes a normal row enable signal nre. As a result, when the input address is not the repair address, which means all the decision signals xfsRed_up, xfsRed_dn maintain low level, the normal row enable signal nre is transited from low level to high level. An upper spare row enable signal sre_up is delayed by a first delay unit 14, while a lower spare row enable signal sre_dn is delayed by a second delay unit 15. An upper block selector 16 defines level of an upper block selection signal bsz_up according to the decoding signal bax2<0>, the normal row enable signal nre, the spare row enable signal sre_dn delayed through the second delay unit 15, the initiated signal wlcz, and the decision signal xfsRed_up. On the other hand, a lower block selector 17 defines level of a lower block selection signal bsz_dn according to the decoding signal bax2<1>, the normal row enable signal nre, the upper spare row enable signal sre_up delayed through the first delay unit 14, the initiated signal wlcz, and the decision signal xfsRed_dn.
As FIG. 2 is a circuit diagram illustrating a block selector of the conventional block selection circuit, an upper block selector and a lower block selector are composed as the same circuit, respectively.
A first PMOS transistor P21 is connected between a power source terminal Vdd and a first node Q21, which is driven according to the initiated signal wlcz. A first NMOS transistor N21 is connected between the first node Q21 and a second node Q22, which is driven according to the initiated signal wlcz. A second NMOS transistor N22 driven by a decoding signal bax and a third NMOS transistor N23 driven by a normal row enable signal nre are serially connected between the second node Q22 and a ground terminal Vss. A fourth NMOS transistor N24 driven by a decision signal xfsRed, which is outputted from the fuse block, and a fifth NMOS transistor N25 driven by another spare row enable signal sre_other are serially connected between the second node Q22 and the ground terminal Vss. However, the second NMOS transistor N22 and the third NMOS transistor N23 connected in series, and the fourth NMOS transistor N24 and the fifth NMOS transistor N25 connected in series are connected in parallel. Here, when a block selector is the upper block selector, the spare row enable signal sre_other is a lower spare row enable signal sre_dn. Contrarily, when the block selector is the lower block selector, the spare row enable signal sre_other is an upper spare row enable signal sre_up. Additionally, a potential of the first node Q21 becomes level of a block selection signal bsz.
An operation of a block selector comprised as aforementioned structure will be illustrated with reference to FIGS. 1 and 2 as follows.
As the first PMOS transistor P21 is turned on and the first NMOS transistor N21 is turned off in accordance with the initiated signal wlcz of low level, the first node Q21 maintains a potential of high level in an initial state. When the initiated signal wlcz is applied to high level, the first PMOS transistor P21 is turned off, and the first NMOS transistor N21 is turned on. Accordingly, a current path is decided by operations of the second NMOS transistor N22 and the third NMOS transistor N23 or the fourth NMOS transistor N24 and the fifth NMOS transistor N25, and thus the potential of the first node Q21 is decided thereby. The second NMOS transistor N22 is operated and also the block is selected by the decoding signal bax2<0:1> for selecting a block. Moreover, the third NMOS transistor is driven by the normal row enable signal nre. During this, when the repair address set according to fuse cutting states of the first and second fuse blocks 11, 12 is not identical to any of external addresses, the normal row enable signal nre is inputted to high level. When the repair address is identical to at least one of external addresses, the normal row enable signal nre is inputted to low level. Meanwhile, the fourth NMOS transistor N24 is driven by the decision signal xfsRed outputted from the fuse blocks 11, 12. During this, when an input address is the repair address, the decision signal xfsRed is inputted to high level, and inputted to low level when the input address is not the repair address. Furthermore, the fifth NMOS transistor N25 is driven by another spare row enable signal sre_other. During this, when the decision signal xfsRed is inputted to high level, a transition time of the block selection signal bsz is set to according to the transition time of another spare row enable signal sre_other. The current path through the second and third NMOS transistors N22, N23 is a current path in case that the normal block is selected, and the current path through the fourth and fifth NMOS transistors N24, N25 is a current path in case that the repair block is selected.
As FIGS. 3A and 3B are waveform diagrams illustrating results when a normal block is selected by using the conventional block selection circuit, FIG. 3A is a waveform diagram of the upper block selector when the upper block is selected by an external address, FIG. 3B is a waveform of the lower block selector at this time.
Referring to FIGS. 1, 2 and 3A, as the decoding signal bax2<0> is transited to high level in order to select the upper block, the second NMOS transistor N22 in the upper block selector is turned on. While this, because the normal row enable signal nre is transited to high level, the third NMOS transistor N23 is turned on. As a result, currents are passed through the second and third NMOS transistors N22, N23 and then the potential of the first node Q21 becomes low level, which potential, as an upper block selection signal bsz_up, selects the upper block.
Referring to FIGS. 1, 2, and 3B, because the decoding signal bax2<1> is applied to low level, the second NOMS transistor N22 in the lower block selector is turned off. Moreover, the decision signal xfsRed_dn outputted from the second fuse block 12 is applied to low level, turning off the fourth NMOS transistor N24, while the upper spare row enable signal sre_up is applied to low level, turning off the fifth NMOS transistor N25. Thereby, the lower block selection signal bsz_dn is outputted to high level and then the lower block is not selected.
However, if the specific row word lines set by the decoding signal bax2<0:1> and the decoding signal bax01<0:3> have defected and are replaced with redundancy word lines of another block, a position of the block decided by an external address doesn't make any meaning but a block address of the replaced redundancy word lines has an important meaning. When the external address is inputted to a word line of the lower block but the word line is replaced with the upper block redundancy word lines, the block selection circuit has to select the upper block according to an operation of the fuse block, however, in this case, the block selection circuit selects a block regardless of the decoding signal bax2<0:1>, which case will be described in FIGS. 4A and 4B.
As FIGS. 4A and 4B are waveform diagrams illustrating results when a repair block is selected by using the conventional block selection circuit, FIG. 4A is a waveform diagram of the upper block selector in the case that the upper block is selected and FIG. 4B is a waveform of a lower block selector at this time.
Referring to FIGS. 1, 2, and 4A, because the input address is identical to the repair address, the normal row enable signal nre is applied to low level, turning off the third NMOS transistor N23. Furthermore, the decision signal xfsRed_up outputted from the first fuse block 11 is applied to high level, turning on the fourth NMOS transistor N24. During this, as the decision signal xfsRed_dn outputted from the second fuse block 12 is outputted to low level, the lower spare row enable signal sre_dn is applied to high level, turning on the fifth NMOS transistor N25. Accordingly, currents are passed through the fourth and fifth NMOS transistors N24, N25 and then a potential of the first node Q21 becomes low level, which potential, as the upper block selection signal bsz_up, selects the upper block.
Referring to FIGS. 1, 2, and 4B, because the input address is identical to the repair address, the normal row enable signal nre is applied to low level, turning off the third NMOS transistor N23. Also, the decision signal xfsRed_dn outputted from the second fuse block 12 is transited to low level, turning off the fourth NMOS transistor N24. While this, as the decision signal xfsRed_up outputted from the first fuse block 11 is applied to high level, the upper spare row enable signal sre_up is applied to low level, turning off the fifth NMOS transistor N25. As a result, the first node Q21, as a selection signal bsz_dn of the lower block, is outputted to high level.
As FIGS. 5A and 5B are waveform diagrams explaining the reason why delay units to delay a spare row enable signal sre are necessary in the conventional block selection circuit, with which illustrates waveform diagrams in the case that the normal block is selected by using FIGS. 3A and 3B
When a signal selecting the upper block is inputted, the upper block selector normally operates. However, the decision signals xfsRed outputted from the fuse block 11, 12 are outputted with different speed, respectively, according to the input address. For instance, when the decision signal xfsRed_dn outputted from the second fuse block 12 is transited to low level later, and the decision signal xfsRed_up outputted from the first fuse block 11 transits to high level earlier, both the upper spare row enable signal sre_up, and the decision signal xfsRed_dn outputted from the second fuse block 12 all become high level, and thus the lower block selection signal bsz_dn is transited to low level as shown in FIG. 5. In this case, however, both the upper and lower blocks are selected. Therefore, the conventional block selection circuit should comprise a first delay unit 14 and a second delay unit 15 which delay the spare row enable signal sre, in order to prevent defect caused due to the difference of outputting speeds of decision signals xfsRed outputted from the first and second fuse blocks 11, 12. However, these delay units degrades an operating speed of the block selection circuit.
As a result, as blocks are selected by using the decision signals xfsRed which depends on the external address, delay units are necessary to compensate outputting speeds of the decision signals xfsRed in the conventional block selection circuit. The delay units cause degradation of the operating speed of the block selection circuit. As well, in order to set a delay time by a simulation, differences should be detected between a decision signal outputted from the rapidest fuse block and another decision signal outputted from the slowest fuse block, in all the case of addresses. Furthermore, because variations of a process, a temperature, and a power source voltage have different influences on output signals of fuse blocks and on a delay circuit, an additional delay time should be considered for circuit designing and it also degrades the operation speed of the block selection circuit.